This application claims the priority benefit of Taiwan application serial No. 89111825, filed Jun. 16, 2000, and Taiwan application serial No. 87119245, filed Nov. 20, 1998.
1. Field of Invention
The present invention relates to a cache system and a method of synchronization data transmission. More particularly, the present invention relates to a cache system in a peripheral device interface control chip cache for synchronization data communication.
2. Description of Related Art
Although data buffers are frequently employed inside a peripheral device interface control chip to process read-out data, cache memory functions are mostly absent. Therefore, whenever peripheral devices need to recall data from a memory unit, the peripheral device interface control chipset must execute a read command and retrieve the relevant data from the memory unit.
FIG. 1 is a conventional timing diagram showing a portion of the peripheral device bus signals during a session when data is read from an external device to a peripheral device. As shown in FIG. 1, two batches of data are transmitted through the peripheral device bus. The two batches of data are transmitted starting at clock cycle CLK1 and CLK20 respectively.
Starting at clock cycle CLK1, a FRAME signal is activated to indicate the initialization of data transmission. In the meantime, destination address of the target device for receiving the transmission data is put on the AD signal lines of bus. In clock cycle CLK2, an IRDY signal is activated to indicate readiness of transmission data of the peripheral device. However, the target is not yet ready to receive the transmission data and the transmission has to wait until the target ready signal TRDY arrives at clock cycle CLK8. Therefore, actual transmission is carried out only at the start of clock cycle CLK9. The period starting from the activation of the IRDY signal to the point just before the activation of the TRDY signal is known as a latency period.
In FIG. 1, the transmission of the second batch of data starts at clock cycle CLK20 when a FRAME signal is activated. The second batch of data is similar to the first batch of data or differs from the first batch by a single line. In other words, the second batch of data may be within a 32-byte address. Hence, control and signal timing of the signal bus by the peripheral device interface controller is similar to the transmission of the first batch of data.
Starting at clock cycle CLK20, a FRAME signal is activated to indicate the initialization of data transmission. In the meantime, destination address of the target device for receiving the transmission data is put on the AD signal lines of the bus. In clock cycle CLK21, an IRDY signal is activated to indicate readiness of transmission data of the peripheral device. However, the target is not yet ready to receive the transmission data and the transmission has to wait until the target ready signal TRDY arrives at clock cycle CLK27. Therefore, actual transmission is carried out only at the start of clock cycle CLK28.
In brief, in conventional data transmission between two peripheral devices through an interface, although two consecutive batches of data have the same target address or differ just by a single line, a latency period is created in each transmission period. The extra latency period will lead to a slow down of the peripheral device interface and a reduction in the efficiency of peripheral device bus and peripheral device.
Accordingly, one object of the present invention is to provide a peripheral device interface control chip having a cache system therein for synchronization data communication with external devices. The cache system inside the control chip is capable of reducing latency period when data are read by a peripheral device, so that utilization of the peripheral device and the peripheral device bus is increased. Furthermore, correctness of transmitted data is further ensured through a data synchronization method.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a peripheral device interface control chip having a cache system in a computer system. The computer system includes a set of memory units, a central processing unit (CPU), a CPU bus, a peripheral device bus and at least one peripheral device. The cache system includes a data buffer and a peripheral device interface controller. The data buffer is located within the control chip for holding a data stream read from the memory so that data required by the peripheral device are provided. In addition, if the data stream is synchronous to the data in the corresponding address within the memory, the data stream is retained. When any one of the peripheral devices demands data already in the data stream, data within the data stream can be immediately provided by the data bufferso that latent period for retrieving the data stream from memory again is reduced.
The peripheral device controller is also installed within the control chip. The controller is used for determining if the data stream includes data demanded by a particular peripheral device, determining if the data stream is synchronous to the data in the corresponding address, retrieving the data stream from memory and putting the data in a data buffer, and switching the state of that portion of the data buffer having data stream therein.
This invention also provides a method of synchronization data transmission between a cache inside a peripheral device interface control chip and an external device. The method can be applied to a computer system having a set of memory unit, at least one central processing unit, a control chip, a peripheral device bus, a CPU bus and at least one peripheral device. The control chip includes a peripheral device interface controller and a data buffer. Furthermore, when data stream within memory is read into the data buffer, the data stream becomes a buffer data stream.
The data synchronization method includes the following steps. On initialization, the data buffer is set to an empty state. When the peripheral device interface controller reads a buffer data stream into the data buffer according to the requirement of a particular peripheral device, the buffered data portion of the data buffer that includes the buffer data stream is set to a clean-unaccessed state. If the peripheral device interface controller detects from the CPU bus a write or a read operation using the corresponding address when the said buffered data portion is in a clean-unaccessed state, the buffered data portion is set to a dirty-unaccessed state.
In addition, If the peripheral device interface controller detects from the peripheral device bus a write operation using the corresponding address when the buffered data is in the clean-unaccessed state, the buffered data portion is set to a dirty-unaccessed state.
If the particular peripheral device that demands the buffer data stream reads the buffer data stream from the buffered data portion when the buffered data portion is in the clean-unaccessed state, the buffered data portion is set to a clean-accessed state.
If the particular peripheral device that demands the buffer data stream reads the buffer data stream from the buffered data portion when the buffered data portion is in a dirty-unaccessed state, the buffered data portion is set to an empty state.
Furthermore, if the peripheral device interface controller detects from the CPU bus a read or a write operation using the corresponding address when the buffered data portion is in a clean-accessed state, the buffered data portion is set to an empty state.
If the peripheral device interface controller detects from the peripheral device bus a write operation using the corresponding address when the buffered data portion is in the clean-accessed state, the buffered data portion is set to an empty state.
This invention also provides a peripheral device interface control chip having a cache system therein and a method of synchronization in data transmission with external devices. The method can be applied to a computer system having a set of memory unit, at least one central processing unit, a control chip, a peripheral device bus, a CPU bus and at least one peripheral device. The control chip includes a peripheral device interface controller and a data buffer. The central processing unit uses a MOESI protocol. Documents relating to the techniques and theories behind the operation of MOESI protocol can be found by contacting the following Internet address: xe2x80x9chttp://www.sun.com/microelectronics/datasheets/stp1030/10.htmlxe2x80x9d. When memory data stream within the memory is read into the central processing unit, the memory data stream becomes a cache data stream. On the other hand, when memory data stream is read into the buffer data, the data stream becomes a buffer data stream.
The data synchronization method includes the following steps. First, if the data buffer executes a read operation from an address in memory that corresponds to the cache data stream when the cache data stream is in modified state, then the peripheral device interface controller will inform the central processing unit to set the cache data stream into an owner state.
If the data buffer executes a read operation from the corresponding address when the cache data stream is in an exclusive state, the peripheral device interface controller will inform the central processing unit to set the cache data stream into a shared state.
In brief, this invention utilizes the data buffer inside a control chip to store read-out data as well as other data in neighboring addresses so that latency period of reading data by peripheral devices is greatly reduced. Hence, utilization of peripheral devices and peripheral device bus is increased correspondingly. Furthermore, by using a data synchronization method, correctness of transmitted data is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.